FIG. 9 is a schematic block diagram showing an example of a conventional circuit which produces fixed point data from floating point data and performs Viterbi decoding. The circuit of FIG. 9 includes an optimizing circuit 101 and a Viterbi decoder or Viterbi decoding circuit 102. FIG. 10 is a flow chart used for explaining a method of producing fixed point data from floating point data and performing Viterbi decoding, by using the circuit shown in FIG. 9.
In the conventional example shown in FIG. 9 and FIG. 10, floating point data is inputted to the optimizing circuit 101 (step S101), and the inputted floating point data is first converted into fixed point data by using the following formula (step S102), in the optimizing circuit 101.(input data/MAX data)×2(Viterbi input bit width−1)  (1)where “MAX data” is the maximum data among the inputted floating point data.
The fixed point data converted by the above formula is inputted into the Viterbi decoding circuit 102 (step S103), and, in the Viterbi decoding circuit 102, Viterbi decoding is performed by using the inputted fixed point data (step S104).
Thereafter, the result of Viterbi decoding obtained in step S104 is outputted from the Viterbi decoding circuit 102 (step S105).
However, in the above-mentioned conventional circuit, it is necessary to provide a division circuit for performing division process in the optimizing circuit which produces the fixed point data from the inputted floating point data. Therefore, there is a problem that a circuit scale of the fixed point data generating circuit becomes large.
Also, there is another problem that, since the bit width of Viterbi input data is fixed, it is only possible to improve Viterbi decoding rate within the decoding precision corresponding to the fixed bit width.